1. Field of the Invention
The invention generally relates to semiconductor memory devices, and more particularly, to a semiconductor memory device applicable to a non-volatile semiconductor memory device.
2. Description of the Background Art
FIG. 1 is a block diagram showing the whole structure of a conventional all-cells-at-one-time erasing type of an erasable and programmable read only memory (hereinafter referred to as flash EEPROM).
Referring to FIG. 1, the flash EEPROM comprises a plurality of memory cell arrays 31. Each memory cell array 31 is provided with a column decoder-Y gate 32. There is also a row decoder 33 common to the plurality of memory cell arrays 31. The plurality of column decoder-Y gates 32 have a column address signal applied from a Y address buffer 34. A row address signal is applied to row decoder 33 from an X address buffer 35. A sense amplifier-write driver 36 is connected to each column decoder-Y gate 32 via an input/output line I/O. An input/output buffer 37 is commonly connected to the plurality of sense amplifier/write drivers 36.
External chip enable signal CE, write enable signal WE, and output enable signal OE are applied to a control signal input buffer 38. The control signal input buffer 38 applies a control signal to a read/write timing generating circuit 39 in response to these signals. The read/write timing generating circuit 39 generates various timing signals in response to the control signal for controlling read/write operation.
Each memory cell array 31 comprises a plurality of memory cells arranged in a matrix manner which is described later. The row decoder 33 selects one row of memory cell array 31 in response to a row address signal applied from X address buffer 35. The column decoder-Y gate 32 selects one column of memory cell array 31 in response to a column address signal applied from Y address buffer 34. Data is read out from the memory cell provided at the intersection of these selected rows and columns to be amplified by a sense amplifier in sense amplifier-write driver 36, and provided via an input/output buffer 37.
FIG. 2 is a circuit diagram showing the structure of one memory cell array 31 included in the flash EEPROM of FIG. 1.
As shown in FIG. 2, a plurality of memory cells MC are arranged in a matrix within memory cell array 31. Bit line BL is connected to each column of the plurality of memory cells MC. The drain of each memory cell MC is connected to the bit line BL. Each bit line BL is connected to the input/output line I/O via the N channel MOS transistor Q31. A plurality of transistors Q31 form the Y gate included in the column decoder-Y gate 32 of FIG. 1. A column decoder 32a included in column decoder-Y gate 32 is connected to the gate of each transistor Q31. A word line WL is provided in each row of the plurality of memory cells MC. The control gate of memory cell MC is connected to each word line WL. The plurality of word lines WL are connected to row decoder 33. The sources of all memory cells MC are connected to ground via source line SL and N channel MOS transistor Q32. An erase signal ERS is applied to the gate of transistor Q32. A current detecting type sense amplifier 40 included in sense amplifier-write driver 36 is connected to input/output line I/O.
FIG. 3 is a sectional view of memory cell MC, while FIG. 4 shows an equivalent circuit of memory cell MC.
Referring to FIG. 3, a source 41 and a drain 42 constituted by N.sup.+ diffusion layer are formed on a P type semiconductor substrate 40. A control gate 44 is provided above the channel region between source 41 and drain 42, with an insulated floating gate 43 between control gate 44 and the channel region. A thin tunnel oxide film 45 of approximately 100.ANG. is formed between floating gate 43 and drain 42. As shown in the equivalent circuit diagram of FIG. 4, memory cell MC is equivalently a memory cell transistor 46 with a variable threshold voltage.
In the memory cell transistor 46, data "1" or "0" is stored depending on whether electrons are stored in floating gate 43 or not. The writing (program) of memory transistor 46 is executed by injecting hot electrons to floating gate 43. When electrons are injected in floating gate 43, the threshold voltage of memory transistor 46 becomes high. This causes the channel region between source 41 and drain 42 to become non-conductive when a predetermined voltage is applied to control gate 44. On the contrary, when electrons are extracted from floating gate 43, the threshold voltage of memory transistor 46 becomes low. This causes the channel region between source 41 and drain 42 to become conductive when a predetermined voltage is applied to control gate 44. By making the positive and negative threshold voltages correspond to data "1" and "0", a non volatile storage is implemented.
The erase, write, and read operation of the flash EEPROM of FIG. 2 will be described.
In the erase operation, high voltage Vpp is applied to all bit lines BL, and all word lines WL are connected to ground, as shown in FIG. 5. At this time, erase signal ERS is brought to the "L" level so that transistor Q32 becomes non-conductive, to hold source line SL at a floating state. Accordingly, the electrons stored in floating gate 43 of the memory transistor are pulled by drain 42 due to tunnel phenomenon, as shown in FIG. 6. As a result, the threshold voltage of the memory transistor becomes low. Thus, the erase of data stored in all memory cells MC is carried out at one time.
In write operation, a high voltage Vpp is applied to the selected bit line BL and the selected word line WL, as shown in FIG. 7. At this time, erase signal ERS is high. As a result, transistor Q32 is turned on, and source line SL is connected to ground. This causes avalanche breakdown in the vicinity of drain 42 of the memory transistor, so that hot electrons are injected to floating gate 43, as shown in FIG. 8. Therefore, the threshold voltage of the memory transistor becomes high. Thus, data is written into the memory cell enclosed with the broken line in FIG. 7.
The read operation of the flash EEPROM will be described. Referring to FIG. 2, one of the plurality of word lines WL is selected by row decoder 33, to which a potential of "H" level is applied. One of the plurality of transistors Q31 is selected by column decoder 32a, to which a potential of "H" is applied to the gate thereof. Thus, one memory cell MC is selected in the above manner. A current detecting type sense amplifier 40 connected to input/output line I/O detects whether current flows from the drain to the source of the selected memory cell MC or not.
Current will not flow through the unselected memory cells MC having a low threshold voltage, because a potential of the "L" level is applied to the control gate of the unselected memory cell MC.
FIG. 9 shows the circuit diagram of the current detecting type sense amplifier 40 of FIG. 2. This current detecting type sense amplifier 40 is shown in Japanese Patent Laying-Open No. 62-170097, for example.
The sense amplifier 40 comprises a current-voltage conversion circuit 40a for converting the current corresponding to the data stored in memory cell MC into voltage, and an inverting circuit 40b for inverting the converted voltage signal. The current-voltage conversion circuit 40a comprises P channel MOS transistors Q41, Q42, and N channel MOS transistors Q43, Q44, and Q45.
In read operation, when memory cell MC turns to a conductive state, the potential of node N11 becomes approximately 1.0V at a steady state. This causes transistor Q43 to be turned on slightly and the potential of node N12 becomes approximately 2V. Consequently, transistors Q44 and Q45 are turned on slightly. However, the potential of node N13 will attain substantially the same level of the potential of node N11 (i.e 1.0V), because the ON resistance of transistor Q42 is set to be much higher than the ON resistance of transistor Q45.
When the memory cell MC is turned to a non-conductive state in read operation, the potential of node N11 becomes approximately 1.1V. This causes the potential of node N12 to be approximately 1.8V so that the potential difference between the gates and sources of transistors Q44 and Q45 becomes approximately 0.7V. Consequently, transistors Q44 and Q45 are turned off to raise the potential of node N13 to 5V.
Thus the reading of data in a conventional flash EEPROM is performed by sensing whether or not current flows through the selected memory cell. However, in the reading operation, when a high potential is applied to bit line BL, a high electric field is applied to the tunnel oxide film 45, resulting in the problem that electrons stored in floating gate 43 leak away. Therefore, the potential of drain 42 had to be suppressed to approximately 1-2V. For the purpose of sensing the current flowing through the memory cell while suppressing the drain potential, a current detecting type sense amplifier 40 was employed.
The current detecting type sense amplifier 40 has a complicated circuit structure, as shown in FIG. 9. The layout area of the current detecting type sense amplifier 40 is large, resulting in difficulty in arrangement by each bit line. Consequently, a conventional flash EEPROM is implemented with a structure in which the memory cell array is divided into a plurality of blocks with the current detecting type sense amplifier arranged in each block, as shown in FIG. 1. However, this structure has the problem of difficulty in realizing high speed read out mode such as the so-called page read out mode (the mode of reading out the data of all memory cells connected to one word line WL at one time) of a DRAM.
A semiconductor memory device using a differential amplifying circuit is disclosed in Japanese Patent Laying-Open No. 61-73305. The semiconductor memory device has one pair of bit lines 51 and 52 connected to either side of a differential amplifying circuit 59, as shown in FIG. 10A. Bit line 51 has a plurality of memory cells 55A (only one memory cell is shown in the figure) and one dummy cell 58A connected, while bit line 52 has a plurality of memory cells 55B (only one memory cell is shown in the figure) and one dummy cell 58B connected.
At the time of reading, bit lines 51 and 52 are charged to supply potential Vdd. When one of the memory cells 55A connected to bit line 51 is selected, the dummy cell 58B connected to bit line 52 is simultaneously selected. Accordingly, if data "1" is stored in the selected memory cell 55A, the potential of bit line 51 remains at supply potential Vdd. If data "0" is stored in the selected memory cell 55A, the potential of bit line 51 is discharged to ground potential. The conductance of dummy cells 58A and 58B is set to be lower than that of memory cells 55A and 55B storing data "0", and also set to be larger than the conductance of memory cell 55A and 55B storing data "1". Therefore, though the potential of bit line 52 is discharged when dummy cell 58A is selected, the potential change of bit line 52 is slower than the potential change when data "0" is read out to bit line 51. This causes difference in the potentials between bit lines 51 and 52, wherein this potential difference undergoes differential amplifying by a differential amplifying circuit 59.
The differential amplifying circuit 59 can be arranged for each bit line because the circuit structure is relatively simple in comparison with the current detecting type sense amplifier 50 shown in FIG. 9. Therefore, the semiconductor memory device of FIG. 10A does not have the problems seen in the conventional EEPROM of FIGS. 1 and 2.
However, the semiconductor memory device of FIG. 10A has a problem due to the fact that the differential amplifying circuit 59 has to be arranged in the middle of the memory cell array. The differential amplifying circuit 59 is generally connected to the input/output line of data, to which the data input/output pins provided in the periphery of the semiconductor chip must be connected. Therefore, in the case where a semiconductor memory device as shown in FIG. 10A has to have the differential amplifying circuit 59 arranged in the middle of the memory cell array, the input/output line of the data becomes long, leading to the difficulty in the layout for wiring. It is appreciated from FIG. 10B that the semiconductor memory device of FIG. 10A requires differential amplifying circuit 59, as well as column decoder 54, and transfer gates 53A and 53B to be provided for each bit line. However, the pitch between each bit line (the pitch in the vertical direction of FIG. 10B) is liable to become narrow in accordance with increase in integration density. It was therefore difficult to arrange differential amplifying circuit 59, column decoder 54, and transfer gates 53A and 53B in such narrow pitches.
Furthermore, in the semiconductor memory device of FIG. 10A, the conductance of dummy cells 58A and 58B must be set to a half of the conductance of memory cells 55A and 55B. Such parameter settings of dummy cells 58A and 58B are difficult under the manufacturing technology.
Also, bit lines 51 and 52 are precharged to supply potential Vdd (approximately 5V), prior to the reading of data in the semiconductor memory device of FIG. 10A. This means that supply potential Vdd is applied to the drains of memory cells 55A and 55B to increase the potential difference between the floating gate storing electrons and the drain. As a result, electrons are pulled from the floating gate to the drain by tunnel phenomenon causing undesired effect on the data holding characteristics of memory cells 55A and 55B.